The present invention is generally directed to a system and method for maintaining optimal timing in interleaved analog-to-digital conversion. More specifically, the subject system and method provide for adaptive self-calibration to remove error in the timing of samples taken for the time-interleaved analog-to-digital conversion of a signal. The subject system and method adaptively detect timing skew based on the outputs of a plurality of analog-to-digital converter (ADC) channels, and does so in a computationally optimized manner for scalable application of the self-calibration to increasingly high sampling rate cases requiring increased multiplicity of interleaved channels.
With ongoing advances in device technologies, there is ever increasing demand for greater speed in circuit operations, such as in the conversion of analog signals to digital form. Where the required conversion rate exceeds the capabilities of one ADC, a plurality of parallel interleaved ADCs have been used in the art to effectively achieve the required conversion rate. A plurality of ADC channels are operated in parallel to each convert a segment of a given analog signal. The ADC channels are synchronized to a common sampling clock, but in mutually phase-offset manner within each cycle of ADC operation (or ‘sampling cycle’), so that they are timed accordingly to sample and convert their different respective signal segments. The effective sampling rate may be increased by increasing the number of ADC channels participating in this process, to in turn increase the number of sample segments within one sampling cycle.
Such parallel interleaved ADC architectures, however, are prone to errors due to mismatches in the offsets, gains, and sampling aperture timing of individual converter channels. That is, the precise instant in time that each ADC channel actually samples within a particular sample segment of the analog signal may be skewed due to various real world factors when actually implemented and used. This results in non-uniform sample timing within the sample segments served by different ADC channels, meaning that the channel-to-channel samples are not taken at uniform time intervals. Yet, such uniformity is presumed when the analog signal is reconstructed from the individual samples, leading to inaccurate digital conversion due to this sample timing mismatch.
Attempts have been made in the art to eliminate or reduce the effects of these types of errors between channels, by calibrating the offsets and gains of ADCs in interleaved topologies. FIG. 1 illustrates a more or less ‘brute force’ approach to eliminating sampling clock timing errors in a parallel interleaved ADC system. In this approach, a time interleaving ADC topology is served by a global front-end sample-and-hold amplifier (SHA) 101. The front-end SHA 101 samples the input analog signal at the full speed of the ADC. Each ADC channel has its own sample-and-hold circuit (each with a clock-driven sample switch 102 and hold capacitor 103) that samples the analog signal at its input, and keeps the sample constant during the full conversion time of the channel's ADC 104. Each individual ADC runs at a clock rate equal to the overall conversion rate divided by the number of channels N, and recursively processes one of every N samples made available by the front-end SHA 101. Because the signal made available by the SHA 101 is held constant in value at its output throughout the sample segment time window for each ADC channel, any timing skew in an individual channel's sampling switch clocking does not affect the value that the channel actually samples. Consequently, any timing skew in the individual channels is ineffectual to the accuracy of the entire system.
This may offer a practicable solution for certain applications (for example, those requiring sampling rates of no more than several GHz and resolution of 10-11 bits), but it does not in many others. The SHA 101 in this approach must be operated at the full speed of overall ADC conversion. Where higher sampling rates are required, therefore, either the power consumption of such SHA is prohibitively excessive, or a fast enough SHA 101 is beyond the limits of known nano-electronic fabrication technologies. The sampling clock timing skew problem must be addressed by other measures.
Calibration processes are known in the art toward that end, but these known calibration processes generally suffer from a general lack of consistent accuracy and efficiency. In certain known approaches, for example, one or more channels are utilized for the acquisition of calibration-specific data. In other known approaches, the calibration is specific to a particular parallel channel configuration, and cannot be readily scaled for effective use in other configurations employing different numbers of ADC channels. In still other approaches, the computations prescribed for multi-channel are complex and yield an excessive processing burden.
There is therefore a need for a system and method by which the timing skew problem is suitably remedied by calibration in a time interleaved ADC system. There is a need for such system and method which carries out effective self-calibration without hindering the conversion operation of the given ADC channels, and which is readily scalable to different applications employing a varying multiplicity of ADC channels.